Parity Generator and Checker

What is the meaning of parity?

The meaning of parity is “equality” or “equivalence”.  So from this meaning, we can understand the use of parity bit in the combinational logic circuits. We use parity bit in the combinational circuits to check whether the input data at the transmission end and receiving end are equal or not.

Purpose of using parity bit in combinational circuits

All of the Data transmission in the digital systems does not occur without any distortion or noise during transmission. So we lose some data or information through our way. Some of our 1s changes into 0s during transmission and some of our 0s changes into 1s. So to overcome this error or problem, we use parity bit in our combinational logic circuits.

What parity bit does?

Parity bit converts the numbers of 1s of the data, into even numbers of 1s or the odd number of ones. If there are even numbers of 1s in the data then parity bit will be 0 and if there are odd numbers of 1s in the data then parity bit will be 1. So parity bit combined with the information or data is transmitted through the channel towards the receiving end. At the receiving end, we check whether the data have the same numbers of 1s, as parity bit says. If numbers of 1s are odd and the parity bit is 0 then it means there is an error in the information.

Parity Generator and Parity checker

A parity generator is a circuit that is used to generate a parity bit for the transmission end so that it can be combined with it. While parity checker is the circuit which is used to check whether parity bit matches the receiving information.

Parity Generator Explanation:-

In parity generator combinational circuit, we give n-1 number of inputs to it, n-1 means one less than n. one less is because that one is a parity bit, that parity generator circuit is going to generate. There are two types of Parity generator.

1. Even parity Generator
2.  Odd parity Generator

Even parity generator

In even parity generator, the aim is to convert all number of 1s in the data stream to the even numbers. How we are going to do this? We are going to do this by functioning parity. So that it gives “1” when there are the odd numbers of ones. And it gives ”0” when there are even numbers of ones. Below is the truth table of this.

Truth Table

So using K-map rule to simplify this truth table,

$$ X=A↖{-} B↖{-}C↖{} +A↖{-} B↖{} C↖{-}+A↖{} B↖{-}C↖{-}+A↖{}B↖{}C↖{} $$
$$ X=A↖{-} (B↖{-}C↖{}+B↖{} C↖{-})+A (B↖{-} C↖{-}+B↖{}C) $$
$$ X= \ov A(B ⊕C)+A \ov{ (B⊕C)} $$
$$ X=A⊕B⊕C $$

Circuit

So we can implement this equation by using two X-OR gates. Below the logic circuit is shown for the even parity generator.

Odd parity generator

In odd parity generator, the aim is to convert all number of 1s in the data stream to the odd numbers. How we are going to do this? We are going to do this by functioning parity bit. So that it gives “1” when there are even numbers of ones. And it gives ”0” when there are odd numbers of ones. Below is the truth table of this.

Truth Table

So using K-map rule to simplify this table,

$$ X=(A⊕B) \ X\NOR\ C $$

Circuit

We can implement this equation by using one X-OR gate and one X-nor gate. Below the logic circuit for the odd parity generator is shown below.

Parity Checker Explanation:

Parity checker circuit is present at the receiving end, it is used to check whether there is an error or not in the received information. In this circuit, we have 4-Bit of the message received. That includes 3-bit of message and 1-bit of parity bit which was generated by the parity generator (in parity generator we have 3-bit of data and then we get a parity bit at the output).  Like parity generator, it has also two types.

1. Even parity checker
2. Odd parity checker

Even parity checker

In even parity checker there must be even number of “1s” in the input. If there are even numbers of “1s” in input, that means our information is error-free, but if there are odd numbers of “1s” that means there is an error in the received information.

So we will design a truth table in which our parity checker bit (which is our output) will be “high” if there are even numbers of “1s” in the input otherwise parity bit checker will be “low” if there are odd numbers of ones. The truth table is shown below.

Truth Table

Using K-map to simplify this truth table,

$$ X = \ov {A B}\ (\ov C D + C\ov D ) + \ov A B\ (\ov {C D} + C D ) + A B\ (\ov C D + C\ov D ) + A \ov B \( \ov{C D} + C D ) $$
$$ \ov{A B}\ ( C ⊕ D) + \ov A B\ (\ov{ C ⊕ D}) + A B\ ( C ⊕ D) + A \ov B( \ov{C ⊕ D}) $$
$$ X = (\ov {A B} + A B)\ ( C ⊕ D) + (\ov A B + A\ov B )\ (\ov {C ⊕ D}) $$
$$ X = (A ⊕B) ⊕ ( C ⊕ D) $$

Circuit

We can implement the above equation by using three X-OR gates. If the number of input bits increases from 4-bit to 5-bit then we can increase one more X-OR gate.

Odd parity checker

In odd parity checker, there must be odd number of “1s” in the input. If there are odd numbers of “1s” in input, that means our information is error-free, but if there are even numbers of “1s” that means there is an error in the received information.

So we will design a truth table in which our parity checker bit (which is our output) will be “high” if there are odd numbers of “1s” in the input otherwise parity bit checker will be “low” if there are even numbers of ones. The truth table is shown below.

Truth Table

Using K-map to simplify this truth table,

$$ X = (A\ xnor\ B) \xnor\ (C\ \xnor\ D) $$

Circuit

So by observing the above equation, we can make the odd parity checker by using three X-NOR gates, the circuit is drawn below.